
avl:     file format elf64-littleaarch64


Disassembly of section .init:

00000000004005b8 <_init>:
  4005b8:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  4005bc:	910003fd 	mov	x29, sp
  4005c0:	94000042 	bl	4006c8 <call_weak_fn>
  4005c4:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4005c8:	d65f03c0 	ret

Disassembly of section .plt:

00000000004005d0 <.plt>:
  4005d0:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  4005d4:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xf414>
  4005d8:	f947fe11 	ldr	x17, [x16, #4088]
  4005dc:	913fe210 	add	x16, x16, #0xff8
  4005e0:	d61f0220 	br	x17
  4005e4:	d503201f 	nop
  4005e8:	d503201f 	nop
  4005ec:	d503201f 	nop

00000000004005f0 <exit@plt>:
  4005f0:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  4005f4:	f9400211 	ldr	x17, [x16]
  4005f8:	91000210 	add	x16, x16, #0x0
  4005fc:	d61f0220 	br	x17

0000000000400600 <malloc@plt>:
  400600:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400604:	f9400611 	ldr	x17, [x16, #8]
  400608:	91002210 	add	x16, x16, #0x8
  40060c:	d61f0220 	br	x17

0000000000400610 <__libc_start_main@plt>:
  400610:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400614:	f9400a11 	ldr	x17, [x16, #16]
  400618:	91004210 	add	x16, x16, #0x10
  40061c:	d61f0220 	br	x17

0000000000400620 <__gmon_start__@plt>:
  400620:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400624:	f9400e11 	ldr	x17, [x16, #24]
  400628:	91006210 	add	x16, x16, #0x18
  40062c:	d61f0220 	br	x17

0000000000400630 <abort@plt>:
  400630:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400634:	f9401211 	ldr	x17, [x16, #32]
  400638:	91008210 	add	x16, x16, #0x20
  40063c:	d61f0220 	br	x17

0000000000400640 <puts@plt>:
  400640:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400644:	f9401611 	ldr	x17, [x16, #40]
  400648:	9100a210 	add	x16, x16, #0x28
  40064c:	d61f0220 	br	x17

0000000000400650 <free@plt>:
  400650:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400654:	f9401a11 	ldr	x17, [x16, #48]
  400658:	9100c210 	add	x16, x16, #0x30
  40065c:	d61f0220 	br	x17

0000000000400660 <__isoc99_scanf@plt>:
  400660:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400664:	f9401e11 	ldr	x17, [x16, #56]
  400668:	9100e210 	add	x16, x16, #0x38
  40066c:	d61f0220 	br	x17

0000000000400670 <printf@plt>:
  400670:	d0000090 	adrp	x16, 412000 <exit@GLIBC_2.17>
  400674:	f9402211 	ldr	x17, [x16, #64]
  400678:	91010210 	add	x16, x16, #0x40
  40067c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400680 <_start>:
  400680:	d280001d 	mov	x29, #0x0                   	// #0
  400684:	d280001e 	mov	x30, #0x0                   	// #0
  400688:	aa0003e5 	mov	x5, x0
  40068c:	f94003e1 	ldr	x1, [sp]
  400690:	910023e2 	add	x2, sp, #0x8
  400694:	910003e6 	mov	x6, sp
  400698:	580000c0 	ldr	x0, 4006b0 <_start+0x30>
  40069c:	580000e3 	ldr	x3, 4006b8 <_start+0x38>
  4006a0:	58000104 	ldr	x4, 4006c0 <_start+0x40>
  4006a4:	97ffffdb 	bl	400610 <__libc_start_main@plt>
  4006a8:	97ffffe2 	bl	400630 <abort@plt>
  4006ac:	00000000 	.inst	0x00000000 ; undefined
  4006b0:	00401354 	.word	0x00401354
  4006b4:	00000000 	.word	0x00000000
  4006b8:	00401710 	.word	0x00401710
  4006bc:	00000000 	.word	0x00000000
  4006c0:	00401790 	.word	0x00401790
  4006c4:	00000000 	.word	0x00000000

00000000004006c8 <call_weak_fn>:
  4006c8:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xf414>
  4006cc:	f947f000 	ldr	x0, [x0, #4064]
  4006d0:	b4000040 	cbz	x0, 4006d8 <call_weak_fn+0x10>
  4006d4:	17ffffd3 	b	400620 <__gmon_start__@plt>
  4006d8:	d65f03c0 	ret
  4006dc:	00000000 	.inst	0x00000000 ; undefined

00000000004006e0 <deregister_tm_clones>:
  4006e0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4006e4:	91016000 	add	x0, x0, #0x58
  4006e8:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  4006ec:	91016021 	add	x1, x1, #0x58
  4006f0:	eb00003f 	cmp	x1, x0
  4006f4:	540000a0 	b.eq	400708 <deregister_tm_clones+0x28>  // b.none
  4006f8:	b0000001 	adrp	x1, 401000 <del+0xc0>
  4006fc:	f943d821 	ldr	x1, [x1, #1968]
  400700:	b4000041 	cbz	x1, 400708 <deregister_tm_clones+0x28>
  400704:	d61f0020 	br	x1
  400708:	d65f03c0 	ret
  40070c:	d503201f 	nop

0000000000400710 <register_tm_clones>:
  400710:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400714:	91016000 	add	x0, x0, #0x58
  400718:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  40071c:	91016021 	add	x1, x1, #0x58
  400720:	cb000021 	sub	x1, x1, x0
  400724:	9343fc21 	asr	x1, x1, #3
  400728:	8b41fc21 	add	x1, x1, x1, lsr #63
  40072c:	9341fc21 	asr	x1, x1, #1
  400730:	b40000a1 	cbz	x1, 400744 <register_tm_clones+0x34>
  400734:	b0000002 	adrp	x2, 401000 <del+0xc0>
  400738:	f943dc42 	ldr	x2, [x2, #1976]
  40073c:	b4000042 	cbz	x2, 400744 <register_tm_clones+0x34>
  400740:	d61f0040 	br	x2
  400744:	d65f03c0 	ret

0000000000400748 <__do_global_dtors_aux>:
  400748:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40074c:	910003fd 	mov	x29, sp
  400750:	f9000bf3 	str	x19, [sp, #16]
  400754:	d0000093 	adrp	x19, 412000 <exit@GLIBC_2.17>
  400758:	39416260 	ldrb	w0, [x19, #88]
  40075c:	35000080 	cbnz	w0, 40076c <__do_global_dtors_aux+0x24>
  400760:	97ffffe0 	bl	4006e0 <deregister_tm_clones>
  400764:	52800020 	mov	w0, #0x1                   	// #1
  400768:	39016260 	strb	w0, [x19, #88]
  40076c:	f9400bf3 	ldr	x19, [sp, #16]
  400770:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400774:	d65f03c0 	ret

0000000000400778 <frame_dummy>:
  400778:	17ffffe6 	b	400710 <register_tm_clones>

000000000040077c <stack_clear>:
  40077c:	14000010 	b	4007bc <stack_clear+0x40>
  400780:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400784:	91017000 	add	x0, x0, #0x5c
  400788:	b9400000 	ldr	w0, [x0]
  40078c:	51000401 	sub	w1, w0, #0x1
  400790:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400794:	91018000 	add	x0, x0, #0x60
  400798:	93407c21 	sxtw	x1, w1
  40079c:	f821781f 	str	xzr, [x0, x1, lsl #3]
  4007a0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007a4:	91017000 	add	x0, x0, #0x5c
  4007a8:	b9400000 	ldr	w0, [x0]
  4007ac:	51000401 	sub	w1, w0, #0x1
  4007b0:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007b4:	91017000 	add	x0, x0, #0x5c
  4007b8:	b9000001 	str	w1, [x0]
  4007bc:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007c0:	91017000 	add	x0, x0, #0x5c
  4007c4:	b9400000 	ldr	w0, [x0]
  4007c8:	7100001f 	cmp	w0, #0x0
  4007cc:	54fffda1 	b.ne	400780 <stack_clear+0x4>  // b.any
  4007d0:	d503201f 	nop
  4007d4:	d65f03c0 	ret

00000000004007d8 <stack_empty>:
  4007d8:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4007dc:	91017000 	add	x0, x0, #0x5c
  4007e0:	b9400000 	ldr	w0, [x0]
  4007e4:	7100001f 	cmp	w0, #0x0
  4007e8:	1a9f17e0 	cset	w0, eq  // eq = none
  4007ec:	12001c00 	and	w0, w0, #0xff
  4007f0:	d65f03c0 	ret

00000000004007f4 <push>:
  4007f4:	d10043ff 	sub	sp, sp, #0x10
  4007f8:	f90007e0 	str	x0, [sp, #8]
  4007fc:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400800:	91017000 	add	x0, x0, #0x5c
  400804:	b9400000 	ldr	w0, [x0]
  400808:	7107fc1f 	cmp	w0, #0x1ff
  40080c:	540001ec 	b.gt	400848 <push+0x54>
  400810:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400814:	91017000 	add	x0, x0, #0x5c
  400818:	b9400000 	ldr	w0, [x0]
  40081c:	11000402 	add	w2, w0, #0x1
  400820:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  400824:	91017021 	add	x1, x1, #0x5c
  400828:	b9000022 	str	w2, [x1]
  40082c:	d0000081 	adrp	x1, 412000 <exit@GLIBC_2.17>
  400830:	91018021 	add	x1, x1, #0x60
  400834:	93407c00 	sxtw	x0, w0
  400838:	f94007e2 	ldr	x2, [sp, #8]
  40083c:	f8207822 	str	x2, [x1, x0, lsl #3]
  400840:	52800000 	mov	w0, #0x0                   	// #0
  400844:	14000002 	b	40084c <push+0x58>
  400848:	12800000 	mov	w0, #0xffffffff            	// #-1
  40084c:	910043ff 	add	sp, sp, #0x10
  400850:	d65f03c0 	ret

0000000000400854 <pop>:
  400854:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400858:	91017000 	add	x0, x0, #0x5c
  40085c:	b9400000 	ldr	w0, [x0]
  400860:	7100001f 	cmp	w0, #0x0
  400864:	5400020d 	b.le	4008a4 <pop+0x50>
  400868:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  40086c:	91017000 	add	x0, x0, #0x5c
  400870:	b9400000 	ldr	w0, [x0]
  400874:	51000401 	sub	w1, w0, #0x1
  400878:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  40087c:	91017000 	add	x0, x0, #0x5c
  400880:	b9000001 	str	w1, [x0]
  400884:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400888:	91017000 	add	x0, x0, #0x5c
  40088c:	b9400001 	ldr	w1, [x0]
  400890:	d0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  400894:	91018000 	add	x0, x0, #0x60
  400898:	93407c21 	sxtw	x1, w1
  40089c:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  4008a0:	14000002 	b	4008a8 <pop+0x54>
  4008a4:	d2800000 	mov	x0, #0x0                   	// #0
  4008a8:	d65f03c0 	ret

00000000004008ac <get_node>:
  4008ac:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4008b0:	910003fd 	mov	x29, sp
  4008b4:	d2800400 	mov	x0, #0x20                  	// #32
  4008b8:	97ffff52 	bl	400600 <malloc@plt>
  4008bc:	f9000fa0 	str	x0, [x29, #24]
  4008c0:	f9400fa0 	ldr	x0, [x29, #24]
  4008c4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4008c8:	d65f03c0 	ret

00000000004008cc <return_node>:
  4008cc:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4008d0:	910003fd 	mov	x29, sp
  4008d4:	f9000fa0 	str	x0, [x29, #24]
  4008d8:	f9400fa0 	ldr	x0, [x29, #24]
  4008dc:	97ffff5d 	bl	400650 <free@plt>
  4008e0:	d503201f 	nop
  4008e4:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4008e8:	d65f03c0 	ret

00000000004008ec <left_rotation>:
  4008ec:	d10083ff 	sub	sp, sp, #0x20
  4008f0:	f90007e0 	str	x0, [sp, #8]
  4008f4:	f94007e0 	ldr	x0, [sp, #8]
  4008f8:	f9400400 	ldr	x0, [x0, #8]
  4008fc:	f9000fe0 	str	x0, [sp, #24]
  400900:	f94007e0 	ldr	x0, [sp, #8]
  400904:	b9400000 	ldr	w0, [x0]
  400908:	b90017e0 	str	w0, [sp, #20]
  40090c:	f94007e0 	ldr	x0, [sp, #8]
  400910:	f9400801 	ldr	x1, [x0, #16]
  400914:	f94007e0 	ldr	x0, [sp, #8]
  400918:	f9000401 	str	x1, [x0, #8]
  40091c:	f94007e0 	ldr	x0, [sp, #8]
  400920:	f9400800 	ldr	x0, [x0, #16]
  400924:	b9400001 	ldr	w1, [x0]
  400928:	f94007e0 	ldr	x0, [sp, #8]
  40092c:	b9000001 	str	w1, [x0]
  400930:	f94007e0 	ldr	x0, [sp, #8]
  400934:	f9400400 	ldr	x0, [x0, #8]
  400938:	f9400801 	ldr	x1, [x0, #16]
  40093c:	f94007e0 	ldr	x0, [sp, #8]
  400940:	f9000801 	str	x1, [x0, #16]
  400944:	f94007e0 	ldr	x0, [sp, #8]
  400948:	f9400401 	ldr	x1, [x0, #8]
  40094c:	f94007e0 	ldr	x0, [sp, #8]
  400950:	f9400400 	ldr	x0, [x0, #8]
  400954:	f9400421 	ldr	x1, [x1, #8]
  400958:	f9000801 	str	x1, [x0, #16]
  40095c:	f94007e0 	ldr	x0, [sp, #8]
  400960:	f9400400 	ldr	x0, [x0, #8]
  400964:	f9400fe1 	ldr	x1, [sp, #24]
  400968:	f9000401 	str	x1, [x0, #8]
  40096c:	f94007e0 	ldr	x0, [sp, #8]
  400970:	f9400400 	ldr	x0, [x0, #8]
  400974:	b94017e1 	ldr	w1, [sp, #20]
  400978:	b9000001 	str	w1, [x0]
  40097c:	d503201f 	nop
  400980:	910083ff 	add	sp, sp, #0x20
  400984:	d65f03c0 	ret

0000000000400988 <right_rotation>:
  400988:	d10083ff 	sub	sp, sp, #0x20
  40098c:	f90007e0 	str	x0, [sp, #8]
  400990:	f94007e0 	ldr	x0, [sp, #8]
  400994:	f9400800 	ldr	x0, [x0, #16]
  400998:	f9000fe0 	str	x0, [sp, #24]
  40099c:	f94007e0 	ldr	x0, [sp, #8]
  4009a0:	b9400000 	ldr	w0, [x0]
  4009a4:	b90017e0 	str	w0, [sp, #20]
  4009a8:	f94007e0 	ldr	x0, [sp, #8]
  4009ac:	f9400401 	ldr	x1, [x0, #8]
  4009b0:	f94007e0 	ldr	x0, [sp, #8]
  4009b4:	f9000801 	str	x1, [x0, #16]
  4009b8:	f94007e0 	ldr	x0, [sp, #8]
  4009bc:	f9400400 	ldr	x0, [x0, #8]
  4009c0:	b9400001 	ldr	w1, [x0]
  4009c4:	f94007e0 	ldr	x0, [sp, #8]
  4009c8:	b9000001 	str	w1, [x0]
  4009cc:	f94007e0 	ldr	x0, [sp, #8]
  4009d0:	f9400800 	ldr	x0, [x0, #16]
  4009d4:	f9400401 	ldr	x1, [x0, #8]
  4009d8:	f94007e0 	ldr	x0, [sp, #8]
  4009dc:	f9000401 	str	x1, [x0, #8]
  4009e0:	f94007e0 	ldr	x0, [sp, #8]
  4009e4:	f9400801 	ldr	x1, [x0, #16]
  4009e8:	f94007e0 	ldr	x0, [sp, #8]
  4009ec:	f9400800 	ldr	x0, [x0, #16]
  4009f0:	f9400821 	ldr	x1, [x1, #16]
  4009f4:	f9000401 	str	x1, [x0, #8]
  4009f8:	f94007e0 	ldr	x0, [sp, #8]
  4009fc:	f9400800 	ldr	x0, [x0, #16]
  400a00:	f9400fe1 	ldr	x1, [sp, #24]
  400a04:	f9000801 	str	x1, [x0, #16]
  400a08:	f94007e0 	ldr	x0, [sp, #8]
  400a0c:	f9400800 	ldr	x0, [x0, #16]
  400a10:	b94017e1 	ldr	w1, [sp, #20]
  400a14:	b9000001 	str	w1, [x0]
  400a18:	d503201f 	nop
  400a1c:	910083ff 	add	sp, sp, #0x20
  400a20:	d65f03c0 	ret

0000000000400a24 <rebalance>:
  400a24:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400a28:	910003fd 	mov	x29, sp
  400a2c:	f9000fa0 	str	x0, [x29, #24]
  400a30:	b9002fbf 	str	wzr, [x29, #44]
  400a34:	14000097 	b	400c90 <rebalance+0x26c>
  400a38:	97ffff87 	bl	400854 <pop>
  400a3c:	f9000fa0 	str	x0, [x29, #24]
  400a40:	f9400fa0 	ldr	x0, [x29, #24]
  400a44:	b9401800 	ldr	w0, [x0, #24]
  400a48:	b9002ba0 	str	w0, [x29, #40]
  400a4c:	f9400fa0 	ldr	x0, [x29, #24]
  400a50:	f9400400 	ldr	x0, [x0, #8]
  400a54:	b9401801 	ldr	w1, [x0, #24]
  400a58:	f9400fa0 	ldr	x0, [x29, #24]
  400a5c:	f9400800 	ldr	x0, [x0, #16]
  400a60:	b9401800 	ldr	w0, [x0, #24]
  400a64:	4b000020 	sub	w0, w1, w0
  400a68:	7100081f 	cmp	w0, #0x2
  400a6c:	540006a1 	b.ne	400b40 <rebalance+0x11c>  // b.any
  400a70:	f9400fa0 	ldr	x0, [x29, #24]
  400a74:	f9400400 	ldr	x0, [x0, #8]
  400a78:	f9400400 	ldr	x0, [x0, #8]
  400a7c:	b9401801 	ldr	w1, [x0, #24]
  400a80:	f9400fa0 	ldr	x0, [x29, #24]
  400a84:	f9400800 	ldr	x0, [x0, #16]
  400a88:	b9401800 	ldr	w0, [x0, #24]
  400a8c:	4b000020 	sub	w0, w1, w0
  400a90:	7100041f 	cmp	w0, #0x1
  400a94:	54000241 	b.ne	400adc <rebalance+0xb8>  // b.any
  400a98:	f9400fa0 	ldr	x0, [x29, #24]
  400a9c:	97ffffbb 	bl	400988 <right_rotation>
  400aa0:	f9400fa0 	ldr	x0, [x29, #24]
  400aa4:	f9400800 	ldr	x0, [x0, #16]
  400aa8:	f9400400 	ldr	x0, [x0, #8]
  400aac:	b9401801 	ldr	w1, [x0, #24]
  400ab0:	f9400fa0 	ldr	x0, [x29, #24]
  400ab4:	f9400800 	ldr	x0, [x0, #16]
  400ab8:	11000421 	add	w1, w1, #0x1
  400abc:	b9001801 	str	w1, [x0, #24]
  400ac0:	f9400fa0 	ldr	x0, [x29, #24]
  400ac4:	f9400800 	ldr	x0, [x0, #16]
  400ac8:	b9401800 	ldr	w0, [x0, #24]
  400acc:	11000401 	add	w1, w0, #0x1
  400ad0:	f9400fa0 	ldr	x0, [x29, #24]
  400ad4:	b9001801 	str	w1, [x0, #24]
  400ad8:	14000067 	b	400c74 <rebalance+0x250>
  400adc:	f9400fa0 	ldr	x0, [x29, #24]
  400ae0:	f9400400 	ldr	x0, [x0, #8]
  400ae4:	97ffff82 	bl	4008ec <left_rotation>
  400ae8:	f9400fa0 	ldr	x0, [x29, #24]
  400aec:	97ffffa7 	bl	400988 <right_rotation>
  400af0:	f9400fa0 	ldr	x0, [x29, #24]
  400af4:	f9400400 	ldr	x0, [x0, #8]
  400af8:	f9400400 	ldr	x0, [x0, #8]
  400afc:	b9401800 	ldr	w0, [x0, #24]
  400b00:	b90027a0 	str	w0, [x29, #36]
  400b04:	f9400fa0 	ldr	x0, [x29, #24]
  400b08:	f9400400 	ldr	x0, [x0, #8]
  400b0c:	b94027a1 	ldr	w1, [x29, #36]
  400b10:	11000421 	add	w1, w1, #0x1
  400b14:	b9001801 	str	w1, [x0, #24]
  400b18:	f9400fa0 	ldr	x0, [x29, #24]
  400b1c:	f9400800 	ldr	x0, [x0, #16]
  400b20:	b94027a1 	ldr	w1, [x29, #36]
  400b24:	11000421 	add	w1, w1, #0x1
  400b28:	b9001801 	str	w1, [x0, #24]
  400b2c:	b94027a0 	ldr	w0, [x29, #36]
  400b30:	11000801 	add	w1, w0, #0x2
  400b34:	f9400fa0 	ldr	x0, [x29, #24]
  400b38:	b9001801 	str	w1, [x0, #24]
  400b3c:	1400004e 	b	400c74 <rebalance+0x250>
  400b40:	f9400fa0 	ldr	x0, [x29, #24]
  400b44:	f9400400 	ldr	x0, [x0, #8]
  400b48:	b9401801 	ldr	w1, [x0, #24]
  400b4c:	f9400fa0 	ldr	x0, [x29, #24]
  400b50:	f9400800 	ldr	x0, [x0, #16]
  400b54:	b9401800 	ldr	w0, [x0, #24]
  400b58:	4b000020 	sub	w0, w1, w0
  400b5c:	3100081f 	cmn	w0, #0x2
  400b60:	54000601 	b.ne	400c20 <rebalance+0x1fc>  // b.any
  400b64:	f9400fa0 	ldr	x0, [x29, #24]
  400b68:	f9400800 	ldr	x0, [x0, #16]
  400b6c:	f9400800 	ldr	x0, [x0, #16]
  400b70:	b9401801 	ldr	w1, [x0, #24]
  400b74:	f9400fa0 	ldr	x0, [x29, #24]
  400b78:	f9400400 	ldr	x0, [x0, #8]
  400b7c:	b9401800 	ldr	w0, [x0, #24]
  400b80:	4b000020 	sub	w0, w1, w0
  400b84:	7100041f 	cmp	w0, #0x1
  400b88:	54000241 	b.ne	400bd0 <rebalance+0x1ac>  // b.any
  400b8c:	f9400fa0 	ldr	x0, [x29, #24]
  400b90:	97ffff57 	bl	4008ec <left_rotation>
  400b94:	f9400fa0 	ldr	x0, [x29, #24]
  400b98:	f9400400 	ldr	x0, [x0, #8]
  400b9c:	f9400800 	ldr	x0, [x0, #16]
  400ba0:	b9401801 	ldr	w1, [x0, #24]
  400ba4:	f9400fa0 	ldr	x0, [x29, #24]
  400ba8:	f9400400 	ldr	x0, [x0, #8]
  400bac:	11000421 	add	w1, w1, #0x1
  400bb0:	b9001801 	str	w1, [x0, #24]
  400bb4:	f9400fa0 	ldr	x0, [x29, #24]
  400bb8:	f9400400 	ldr	x0, [x0, #8]
  400bbc:	b9401800 	ldr	w0, [x0, #24]
  400bc0:	11000401 	add	w1, w0, #0x1
  400bc4:	f9400fa0 	ldr	x0, [x29, #24]
  400bc8:	b9001801 	str	w1, [x0, #24]
  400bcc:	1400002a 	b	400c74 <rebalance+0x250>
  400bd0:	f9400fa0 	ldr	x0, [x29, #24]
  400bd4:	f9400800 	ldr	x0, [x0, #16]
  400bd8:	97ffff6c 	bl	400988 <right_rotation>
  400bdc:	f9400fa0 	ldr	x0, [x29, #24]
  400be0:	97ffff43 	bl	4008ec <left_rotation>
  400be4:	f9400fa0 	ldr	x0, [x29, #24]
  400be8:	f9400800 	ldr	x0, [x0, #16]
  400bec:	f9400800 	ldr	x0, [x0, #16]
  400bf0:	b9401800 	ldr	w0, [x0, #24]
  400bf4:	b90027a0 	str	w0, [x29, #36]
  400bf8:	f9400fa0 	ldr	x0, [x29, #24]
  400bfc:	f9400400 	ldr	x0, [x0, #8]
  400c00:	b94027a1 	ldr	w1, [x29, #36]
  400c04:	11000421 	add	w1, w1, #0x1
  400c08:	b9001801 	str	w1, [x0, #24]
  400c0c:	b94027a0 	ldr	w0, [x29, #36]
  400c10:	11000801 	add	w1, w0, #0x2
  400c14:	f9400fa0 	ldr	x0, [x29, #24]
  400c18:	b9001801 	str	w1, [x0, #24]
  400c1c:	14000016 	b	400c74 <rebalance+0x250>
  400c20:	f9400fa0 	ldr	x0, [x29, #24]
  400c24:	f9400400 	ldr	x0, [x0, #8]
  400c28:	b9401801 	ldr	w1, [x0, #24]
  400c2c:	f9400fa0 	ldr	x0, [x29, #24]
  400c30:	f9400800 	ldr	x0, [x0, #16]
  400c34:	b9401800 	ldr	w0, [x0, #24]
  400c38:	6b00003f 	cmp	w1, w0
  400c3c:	5400010d 	b.le	400c5c <rebalance+0x238>
  400c40:	f9400fa0 	ldr	x0, [x29, #24]
  400c44:	f9400400 	ldr	x0, [x0, #8]
  400c48:	b9401800 	ldr	w0, [x0, #24]
  400c4c:	11000401 	add	w1, w0, #0x1
  400c50:	f9400fa0 	ldr	x0, [x29, #24]
  400c54:	b9001801 	str	w1, [x0, #24]
  400c58:	14000007 	b	400c74 <rebalance+0x250>
  400c5c:	f9400fa0 	ldr	x0, [x29, #24]
  400c60:	f9400800 	ldr	x0, [x0, #16]
  400c64:	b9401800 	ldr	w0, [x0, #24]
  400c68:	11000401 	add	w1, w0, #0x1
  400c6c:	f9400fa0 	ldr	x0, [x29, #24]
  400c70:	b9001801 	str	w1, [x0, #24]
  400c74:	f9400fa0 	ldr	x0, [x29, #24]
  400c78:	b9401800 	ldr	w0, [x0, #24]
  400c7c:	b9402ba1 	ldr	w1, [x29, #40]
  400c80:	6b00003f 	cmp	w1, w0
  400c84:	54000061 	b.ne	400c90 <rebalance+0x26c>  // b.any
  400c88:	52800020 	mov	w0, #0x1                   	// #1
  400c8c:	b9002fa0 	str	w0, [x29, #44]
  400c90:	97fffed2 	bl	4007d8 <stack_empty>
  400c94:	7100001f 	cmp	w0, #0x0
  400c98:	54000081 	b.ne	400ca8 <rebalance+0x284>  // b.any
  400c9c:	b9402fa0 	ldr	w0, [x29, #44]
  400ca0:	7100001f 	cmp	w0, #0x0
  400ca4:	54ffeca0 	b.eq	400a38 <rebalance+0x14>  // b.none
  400ca8:	97fffeb5 	bl	40077c <stack_clear>
  400cac:	52800000 	mov	w0, #0x0                   	// #0
  400cb0:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400cb4:	d65f03c0 	ret

0000000000400cb8 <creat_tree>:
  400cb8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400cbc:	910003fd 	mov	x29, sp
  400cc0:	97fffefb 	bl	4008ac <get_node>
  400cc4:	f9000fa0 	str	x0, [x29, #24]
  400cc8:	f9400fa0 	ldr	x0, [x29, #24]
  400ccc:	f900081f 	str	xzr, [x0, #16]
  400cd0:	f9400fa0 	ldr	x0, [x29, #24]
  400cd4:	f9400801 	ldr	x1, [x0, #16]
  400cd8:	f9400fa0 	ldr	x0, [x29, #24]
  400cdc:	f9000401 	str	x1, [x0, #8]
  400ce0:	f9400fa0 	ldr	x0, [x29, #24]
  400ce4:	b900181f 	str	wzr, [x0, #24]
  400ce8:	f9400fa0 	ldr	x0, [x29, #24]
  400cec:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400cf0:	d65f03c0 	ret

0000000000400cf4 <find>:
  400cf4:	d10083ff 	sub	sp, sp, #0x20
  400cf8:	f90007e0 	str	x0, [sp, #8]
  400cfc:	b90007e1 	str	w1, [sp, #4]
  400d00:	f94007e0 	ldr	x0, [sp, #8]
  400d04:	f9400400 	ldr	x0, [x0, #8]
  400d08:	f100001f 	cmp	x0, #0x0
  400d0c:	54000061 	b.ne	400d18 <find+0x24>  // b.any
  400d10:	d2800000 	mov	x0, #0x0                   	// #0
  400d14:	1400001d 	b	400d88 <find+0x94>
  400d18:	f94007e0 	ldr	x0, [sp, #8]
  400d1c:	f9000fe0 	str	x0, [sp, #24]
  400d20:	1400000d 	b	400d54 <find+0x60>
  400d24:	f9400fe0 	ldr	x0, [sp, #24]
  400d28:	b9400000 	ldr	w0, [x0]
  400d2c:	b94007e1 	ldr	w1, [sp, #4]
  400d30:	6b00003f 	cmp	w1, w0
  400d34:	540000aa 	b.ge	400d48 <find+0x54>  // b.tcont
  400d38:	f9400fe0 	ldr	x0, [sp, #24]
  400d3c:	f9400400 	ldr	x0, [x0, #8]
  400d40:	f9000fe0 	str	x0, [sp, #24]
  400d44:	14000004 	b	400d54 <find+0x60>
  400d48:	f9400fe0 	ldr	x0, [sp, #24]
  400d4c:	f9400800 	ldr	x0, [x0, #16]
  400d50:	f9000fe0 	str	x0, [sp, #24]
  400d54:	f9400fe0 	ldr	x0, [sp, #24]
  400d58:	f9400800 	ldr	x0, [x0, #16]
  400d5c:	f100001f 	cmp	x0, #0x0
  400d60:	54fffe21 	b.ne	400d24 <find+0x30>  // b.any
  400d64:	f9400fe0 	ldr	x0, [sp, #24]
  400d68:	b9400000 	ldr	w0, [x0]
  400d6c:	b94007e1 	ldr	w1, [sp, #4]
  400d70:	6b00003f 	cmp	w1, w0
  400d74:	54000081 	b.ne	400d84 <find+0x90>  // b.any
  400d78:	f9400fe0 	ldr	x0, [sp, #24]
  400d7c:	f9400400 	ldr	x0, [x0, #8]
  400d80:	14000002 	b	400d88 <find+0x94>
  400d84:	d2800000 	mov	x0, #0x0                   	// #0
  400d88:	910083ff 	add	sp, sp, #0x20
  400d8c:	d65f03c0 	ret

0000000000400d90 <insert>:
  400d90:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d94:	910003fd 	mov	x29, sp
  400d98:	f9000fa0 	str	x0, [x29, #24]
  400d9c:	f9000ba1 	str	x1, [x29, #16]
  400da0:	f9400ba0 	ldr	x0, [x29, #16]
  400da4:	b9400000 	ldr	w0, [x0]
  400da8:	b90037a0 	str	w0, [x29, #52]
  400dac:	b94037a0 	ldr	w0, [x29, #52]
  400db0:	b90033a0 	str	w0, [x29, #48]
  400db4:	f9400fa0 	ldr	x0, [x29, #24]
  400db8:	f9400400 	ldr	x0, [x0, #8]
  400dbc:	f100001f 	cmp	x0, #0x0
  400dc0:	54000181 	b.ne	400df0 <insert+0x60>  // b.any
  400dc4:	f9400fa0 	ldr	x0, [x29, #24]
  400dc8:	f9400ba1 	ldr	x1, [x29, #16]
  400dcc:	f9000401 	str	x1, [x0, #8]
  400dd0:	f9400fa0 	ldr	x0, [x29, #24]
  400dd4:	b94037a1 	ldr	w1, [x29, #52]
  400dd8:	b9000001 	str	w1, [x0]
  400ddc:	f9400fa0 	ldr	x0, [x29, #24]
  400de0:	b900181f 	str	wzr, [x0, #24]
  400de4:	f9400fa0 	ldr	x0, [x29, #24]
  400de8:	f900081f 	str	xzr, [x0, #16]
  400dec:	14000050 	b	400f2c <insert+0x19c>
  400df0:	97fffe63 	bl	40077c <stack_clear>
  400df4:	f9400fa0 	ldr	x0, [x29, #24]
  400df8:	f9001fa0 	str	x0, [x29, #56]
  400dfc:	1400000f 	b	400e38 <insert+0xa8>
  400e00:	f9401fa0 	ldr	x0, [x29, #56]
  400e04:	97fffe7c 	bl	4007f4 <push>
  400e08:	f9401fa0 	ldr	x0, [x29, #56]
  400e0c:	b9400000 	ldr	w0, [x0]
  400e10:	b94033a1 	ldr	w1, [x29, #48]
  400e14:	6b00003f 	cmp	w1, w0
  400e18:	540000aa 	b.ge	400e2c <insert+0x9c>  // b.tcont
  400e1c:	f9401fa0 	ldr	x0, [x29, #56]
  400e20:	f9400400 	ldr	x0, [x0, #8]
  400e24:	f9001fa0 	str	x0, [x29, #56]
  400e28:	14000004 	b	400e38 <insert+0xa8>
  400e2c:	f9401fa0 	ldr	x0, [x29, #56]
  400e30:	f9400800 	ldr	x0, [x0, #16]
  400e34:	f9001fa0 	str	x0, [x29, #56]
  400e38:	f9401fa0 	ldr	x0, [x29, #56]
  400e3c:	f9400800 	ldr	x0, [x0, #16]
  400e40:	f100001f 	cmp	x0, #0x0
  400e44:	54fffde1 	b.ne	400e00 <insert+0x70>  // b.any
  400e48:	f9401fa0 	ldr	x0, [x29, #56]
  400e4c:	b9400000 	ldr	w0, [x0]
  400e50:	b94033a1 	ldr	w1, [x29, #48]
  400e54:	6b00003f 	cmp	w1, w0
  400e58:	54000061 	b.ne	400e64 <insert+0xd4>  // b.any
  400e5c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400e60:	14000036 	b	400f38 <insert+0x1a8>
  400e64:	97fffe92 	bl	4008ac <get_node>
  400e68:	f90017a0 	str	x0, [x29, #40]
  400e6c:	f9401fa0 	ldr	x0, [x29, #56]
  400e70:	f9400401 	ldr	x1, [x0, #8]
  400e74:	f94017a0 	ldr	x0, [x29, #40]
  400e78:	f9000401 	str	x1, [x0, #8]
  400e7c:	f9401fa0 	ldr	x0, [x29, #56]
  400e80:	b9400001 	ldr	w1, [x0]
  400e84:	f94017a0 	ldr	x0, [x29, #40]
  400e88:	b9000001 	str	w1, [x0]
  400e8c:	f94017a0 	ldr	x0, [x29, #40]
  400e90:	f900081f 	str	xzr, [x0, #16]
  400e94:	f94017a0 	ldr	x0, [x29, #40]
  400e98:	b900181f 	str	wzr, [x0, #24]
  400e9c:	97fffe84 	bl	4008ac <get_node>
  400ea0:	f90013a0 	str	x0, [x29, #32]
  400ea4:	f94013a0 	ldr	x0, [x29, #32]
  400ea8:	f9400ba1 	ldr	x1, [x29, #16]
  400eac:	f9000401 	str	x1, [x0, #8]
  400eb0:	f94013a0 	ldr	x0, [x29, #32]
  400eb4:	b94037a1 	ldr	w1, [x29, #52]
  400eb8:	b9000001 	str	w1, [x0]
  400ebc:	f94013a0 	ldr	x0, [x29, #32]
  400ec0:	f900081f 	str	xzr, [x0, #16]
  400ec4:	f94013a0 	ldr	x0, [x29, #32]
  400ec8:	b900181f 	str	wzr, [x0, #24]
  400ecc:	f9401fa0 	ldr	x0, [x29, #56]
  400ed0:	b9400000 	ldr	w0, [x0]
  400ed4:	b94037a1 	ldr	w1, [x29, #52]
  400ed8:	6b00003f 	cmp	w1, w0
  400edc:	5400016d 	b.le	400f08 <insert+0x178>
  400ee0:	f9401fa0 	ldr	x0, [x29, #56]
  400ee4:	f94017a1 	ldr	x1, [x29, #40]
  400ee8:	f9000401 	str	x1, [x0, #8]
  400eec:	f9401fa0 	ldr	x0, [x29, #56]
  400ef0:	f94013a1 	ldr	x1, [x29, #32]
  400ef4:	f9000801 	str	x1, [x0, #16]
  400ef8:	f9401fa0 	ldr	x0, [x29, #56]
  400efc:	b94037a1 	ldr	w1, [x29, #52]
  400f00:	b9000001 	str	w1, [x0]
  400f04:	14000007 	b	400f20 <insert+0x190>
  400f08:	f9401fa0 	ldr	x0, [x29, #56]
  400f0c:	f94013a1 	ldr	x1, [x29, #32]
  400f10:	f9000401 	str	x1, [x0, #8]
  400f14:	f9401fa0 	ldr	x0, [x29, #56]
  400f18:	f94017a1 	ldr	x1, [x29, #40]
  400f1c:	f9000801 	str	x1, [x0, #16]
  400f20:	f9401fa0 	ldr	x0, [x29, #56]
  400f24:	52800021 	mov	w1, #0x1                   	// #1
  400f28:	b9001801 	str	w1, [x0, #24]
  400f2c:	f9401fa0 	ldr	x0, [x29, #56]
  400f30:	97fffebd 	bl	400a24 <rebalance>
  400f34:	52800000 	mov	w0, #0x0                   	// #0
  400f38:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400f3c:	d65f03c0 	ret

0000000000400f40 <del>:
  400f40:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400f44:	910003fd 	mov	x29, sp
  400f48:	f9000fa0 	str	x0, [x29, #24]
  400f4c:	b90017a1 	str	w1, [x29, #20]
  400f50:	f9400fa0 	ldr	x0, [x29, #24]
  400f54:	f9400400 	ldr	x0, [x0, #8]
  400f58:	f100001f 	cmp	x0, #0x0
  400f5c:	54000061 	b.ne	400f68 <del+0x28>  // b.any
  400f60:	12800000 	mov	w0, #0xffffffff            	// #-1
  400f64:	1400004d 	b	401098 <del+0x158>
  400f68:	f9400fa0 	ldr	x0, [x29, #24]
  400f6c:	f9400800 	ldr	x0, [x0, #16]
  400f70:	f100001f 	cmp	x0, #0x0
  400f74:	54000181 	b.ne	400fa4 <del+0x64>  // b.any
  400f78:	f9400fa0 	ldr	x0, [x29, #24]
  400f7c:	b9400000 	ldr	w0, [x0]
  400f80:	b94017a1 	ldr	w1, [x29, #20]
  400f84:	6b00003f 	cmp	w1, w0
  400f88:	540000a1 	b.ne	400f9c <del+0x5c>  // b.any
  400f8c:	f9400fa0 	ldr	x0, [x29, #24]
  400f90:	f900041f 	str	xzr, [x0, #8]
  400f94:	52800000 	mov	w0, #0x0                   	// #0
  400f98:	14000040 	b	401098 <del+0x158>
  400f9c:	12800000 	mov	w0, #0xffffffff            	// #-1
  400fa0:	1400003e 	b	401098 <del+0x158>
  400fa4:	f9400fa0 	ldr	x0, [x29, #24]
  400fa8:	f9001fa0 	str	x0, [x29, #56]
  400fac:	97fffdf4 	bl	40077c <stack_clear>
  400fb0:	14000017 	b	40100c <del+0xcc>
  400fb4:	f9401fa0 	ldr	x0, [x29, #56]
  400fb8:	f9001ba0 	str	x0, [x29, #48]
  400fbc:	f9401ba0 	ldr	x0, [x29, #48]
  400fc0:	97fffe0d 	bl	4007f4 <push>
  400fc4:	f9401fa0 	ldr	x0, [x29, #56]
  400fc8:	b9400000 	ldr	w0, [x0]
  400fcc:	b94017a1 	ldr	w1, [x29, #20]
  400fd0:	6b00003f 	cmp	w1, w0
  400fd4:	5400010a 	b.ge	400ff4 <del+0xb4>  // b.tcont
  400fd8:	f9401ba0 	ldr	x0, [x29, #48]
  400fdc:	f9400400 	ldr	x0, [x0, #8]
  400fe0:	f9001fa0 	str	x0, [x29, #56]
  400fe4:	f9401ba0 	ldr	x0, [x29, #48]
  400fe8:	f9400800 	ldr	x0, [x0, #16]
  400fec:	f90017a0 	str	x0, [x29, #40]
  400ff0:	14000007 	b	40100c <del+0xcc>
  400ff4:	f9401ba0 	ldr	x0, [x29, #48]
  400ff8:	f9400800 	ldr	x0, [x0, #16]
  400ffc:	f9001fa0 	str	x0, [x29, #56]
  401000:	f9401ba0 	ldr	x0, [x29, #48]
  401004:	f9400400 	ldr	x0, [x0, #8]
  401008:	f90017a0 	str	x0, [x29, #40]
  40100c:	f9401fa0 	ldr	x0, [x29, #56]
  401010:	f9400800 	ldr	x0, [x0, #16]
  401014:	f100001f 	cmp	x0, #0x0
  401018:	54fffce1 	b.ne	400fb4 <del+0x74>  // b.any
  40101c:	f9401fa0 	ldr	x0, [x29, #56]
  401020:	b9400000 	ldr	w0, [x0]
  401024:	b94017a1 	ldr	w1, [x29, #20]
  401028:	6b00003f 	cmp	w1, w0
  40102c:	54000060 	b.eq	401038 <del+0xf8>  // b.none
  401030:	12800000 	mov	w0, #0xffffffff            	// #-1
  401034:	14000019 	b	401098 <del+0x158>
  401038:	f94017a0 	ldr	x0, [x29, #40]
  40103c:	b9400001 	ldr	w1, [x0]
  401040:	f9401ba0 	ldr	x0, [x29, #48]
  401044:	b9000001 	str	w1, [x0]
  401048:	f94017a0 	ldr	x0, [x29, #40]
  40104c:	f9400401 	ldr	x1, [x0, #8]
  401050:	f9401ba0 	ldr	x0, [x29, #48]
  401054:	f9000401 	str	x1, [x0, #8]
  401058:	f94017a0 	ldr	x0, [x29, #40]
  40105c:	f9400801 	ldr	x1, [x0, #16]
  401060:	f9401ba0 	ldr	x0, [x29, #48]
  401064:	f9000801 	str	x1, [x0, #16]
  401068:	f9401ba0 	ldr	x0, [x29, #48]
  40106c:	b9401800 	ldr	w0, [x0, #24]
  401070:	51000401 	sub	w1, w0, #0x1
  401074:	f9401ba0 	ldr	x0, [x29, #48]
  401078:	b9001801 	str	w1, [x0, #24]
  40107c:	f9401fa0 	ldr	x0, [x29, #56]
  401080:	97fffe13 	bl	4008cc <return_node>
  401084:	f94017a0 	ldr	x0, [x29, #40]
  401088:	97fffe11 	bl	4008cc <return_node>
  40108c:	97fffdf2 	bl	400854 <pop>
  401090:	97fffe65 	bl	400a24 <rebalance>
  401094:	52800000 	mov	w0, #0x0                   	// #0
  401098:	a8c47bfd 	ldp	x29, x30, [sp], #64
  40109c:	d65f03c0 	ret

00000000004010a0 <travel>:
  4010a0:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4010a4:	910003fd 	mov	x29, sp
  4010a8:	f9000fa0 	str	x0, [x29, #24]
  4010ac:	97fffdb4 	bl	40077c <stack_clear>
  4010b0:	f9400fa0 	ldr	x0, [x29, #24]
  4010b4:	f9400400 	ldr	x0, [x0, #8]
  4010b8:	f100001f 	cmp	x0, #0x0
  4010bc:	54000081 	b.ne	4010cc <travel+0x2c>  // b.any
  4010c0:	f9400fa0 	ldr	x0, [x29, #24]
  4010c4:	97fffdcc 	bl	4007f4 <push>
  4010c8:	1400002c 	b	401178 <travel+0xd8>
  4010cc:	f9400fa0 	ldr	x0, [x29, #24]
  4010d0:	f9400400 	ldr	x0, [x0, #8]
  4010d4:	f100001f 	cmp	x0, #0x0
  4010d8:	54000500 	b.eq	401178 <travel+0xd8>  // b.none
  4010dc:	b9002fbf 	str	wzr, [x29, #44]
  4010e0:	f9400fa0 	ldr	x0, [x29, #24]
  4010e4:	97fffdc4 	bl	4007f4 <push>
  4010e8:	1400001e 	b	401160 <travel+0xc0>
  4010ec:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4010f0:	91018000 	add	x0, x0, #0x60
  4010f4:	b9802fa1 	ldrsw	x1, [x29, #44]
  4010f8:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  4010fc:	f9400400 	ldr	x0, [x0, #8]
  401100:	f100001f 	cmp	x0, #0x0
  401104:	54000280 	b.eq	401154 <travel+0xb4>  // b.none
  401108:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  40110c:	91018000 	add	x0, x0, #0x60
  401110:	b9802fa1 	ldrsw	x1, [x29, #44]
  401114:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  401118:	f9400800 	ldr	x0, [x0, #16]
  40111c:	f100001f 	cmp	x0, #0x0
  401120:	540001a0 	b.eq	401154 <travel+0xb4>  // b.none
  401124:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  401128:	91018000 	add	x0, x0, #0x60
  40112c:	b9802fa1 	ldrsw	x1, [x29, #44]
  401130:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  401134:	f9400400 	ldr	x0, [x0, #8]
  401138:	97fffdaf 	bl	4007f4 <push>
  40113c:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  401140:	91018000 	add	x0, x0, #0x60
  401144:	b9802fa1 	ldrsw	x1, [x29, #44]
  401148:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  40114c:	f9400800 	ldr	x0, [x0, #16]
  401150:	97fffda9 	bl	4007f4 <push>
  401154:	b9402fa0 	ldr	w0, [x29, #44]
  401158:	11000400 	add	w0, w0, #0x1
  40115c:	b9002fa0 	str	w0, [x29, #44]
  401160:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  401164:	91017000 	add	x0, x0, #0x5c
  401168:	b9400000 	ldr	w0, [x0]
  40116c:	b9402fa1 	ldr	w1, [x29, #44]
  401170:	6b00003f 	cmp	w1, w0
  401174:	54fffbc1 	b.ne	4010ec <travel+0x4c>  // b.any
  401178:	52800000 	mov	w0, #0x0                   	// #0
  40117c:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401180:	d65f03c0 	ret

0000000000401184 <test_structure>:
  401184:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  401188:	910003fd 	mov	x29, sp
  40118c:	f9000fa0 	str	x0, [x29, #24]
  401190:	12800000 	mov	w0, #0xffffffff            	// #-1
  401194:	b9002fa0 	str	w0, [x29, #44]
  401198:	f9400fa0 	ldr	x0, [x29, #24]
  40119c:	97ffffc1 	bl	4010a0 <travel>
  4011a0:	14000033 	b	40126c <test_structure+0xe8>
  4011a4:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4011a8:	91017000 	add	x0, x0, #0x5c
  4011ac:	b9400000 	ldr	w0, [x0]
  4011b0:	51000401 	sub	w1, w0, #0x1
  4011b4:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4011b8:	91017000 	add	x0, x0, #0x5c
  4011bc:	b9000001 	str	w1, [x0]
  4011c0:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4011c4:	91017000 	add	x0, x0, #0x5c
  4011c8:	b9400001 	ldr	w1, [x0]
  4011cc:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4011d0:	91018000 	add	x0, x0, #0x60
  4011d4:	93407c21 	sxtw	x1, w1
  4011d8:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  4011dc:	f9400800 	ldr	x0, [x0, #16]
  4011e0:	f100001f 	cmp	x0, #0x0
  4011e4:	540001a1 	b.ne	401218 <test_structure+0x94>  // b.any
  4011e8:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4011ec:	91017000 	add	x0, x0, #0x5c
  4011f0:	b9400001 	ldr	w1, [x0]
  4011f4:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4011f8:	91018000 	add	x0, x0, #0x60
  4011fc:	93407c21 	sxtw	x1, w1
  401200:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  401204:	b9401800 	ldr	w0, [x0, #24]
  401208:	7100001f 	cmp	w0, #0x0
  40120c:	54000061 	b.ne	401218 <test_structure+0x94>  // b.any
  401210:	b9002fbf 	str	wzr, [x29, #44]
  401214:	14000016 	b	40126c <test_structure+0xe8>
  401218:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  40121c:	91017000 	add	x0, x0, #0x5c
  401220:	b9400001 	ldr	w1, [x0]
  401224:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  401228:	91018000 	add	x0, x0, #0x60
  40122c:	93407c21 	sxtw	x1, w1
  401230:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  401234:	f9400400 	ldr	x0, [x0, #8]
  401238:	f100001f 	cmp	x0, #0x0
  40123c:	54000180 	b.eq	40126c <test_structure+0xe8>  // b.none
  401240:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  401244:	91017000 	add	x0, x0, #0x5c
  401248:	b9400001 	ldr	w1, [x0]
  40124c:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  401250:	91018000 	add	x0, x0, #0x60
  401254:	93407c21 	sxtw	x1, w1
  401258:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  40125c:	f9400800 	ldr	x0, [x0, #16]
  401260:	f100001f 	cmp	x0, #0x0
  401264:	54000040 	b.eq	40126c <test_structure+0xe8>  // b.none
  401268:	b9002fbf 	str	wzr, [x29, #44]
  40126c:	97fffd5b 	bl	4007d8 <stack_empty>
  401270:	7100001f 	cmp	w0, #0x0
  401274:	54fff980 	b.eq	4011a4 <test_structure+0x20>  // b.none
  401278:	97fffd41 	bl	40077c <stack_clear>
  40127c:	b9402fa0 	ldr	w0, [x29, #44]
  401280:	a8c37bfd 	ldp	x29, x30, [sp], #48
  401284:	d65f03c0 	ret

0000000000401288 <remove_tree>:
  401288:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  40128c:	910003fd 	mov	x29, sp
  401290:	f9000fa0 	str	x0, [x29, #24]
  401294:	f9400fa0 	ldr	x0, [x29, #24]
  401298:	97ffff82 	bl	4010a0 <travel>
  40129c:	97fffd4f 	bl	4007d8 <stack_empty>
  4012a0:	7100001f 	cmp	w0, #0x0
  4012a4:	540000a0 	b.eq	4012b8 <remove_tree+0x30>  // b.none
  4012a8:	12800000 	mov	w0, #0xffffffff            	// #-1
  4012ac:	14000007 	b	4012c8 <remove_tree+0x40>
  4012b0:	97fffd69 	bl	400854 <pop>
  4012b4:	97fffd86 	bl	4008cc <return_node>
  4012b8:	97fffd48 	bl	4007d8 <stack_empty>
  4012bc:	7100001f 	cmp	w0, #0x0
  4012c0:	54ffff80 	b.eq	4012b0 <remove_tree+0x28>  // b.none
  4012c4:	52800000 	mov	w0, #0x0                   	// #0
  4012c8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  4012cc:	d65f03c0 	ret

00000000004012d0 <help>:
  4012d0:	a9ba7bfd 	stp	x29, x30, [sp, #-96]!
  4012d4:	910003fd 	mov	x29, sp
  4012d8:	90000000 	adrp	x0, 401000 <del+0xc0>
  4012dc:	91228001 	add	x1, x0, #0x8a0
  4012e0:	910043a0 	add	x0, x29, #0x10
  4012e4:	a9400c22 	ldp	x2, x3, [x1]
  4012e8:	a9000c02 	stp	x2, x3, [x0]
  4012ec:	a9410c22 	ldp	x2, x3, [x1, #16]
  4012f0:	a9010c02 	stp	x2, x3, [x0, #16]
  4012f4:	a9420c22 	ldp	x2, x3, [x1, #32]
  4012f8:	a9020c02 	stp	x2, x3, [x0, #32]
  4012fc:	a9430c22 	ldp	x2, x3, [x1, #48]
  401300:	a9030c02 	stp	x2, x3, [x0, #48]
  401304:	f9402021 	ldr	x1, [x1, #64]
  401308:	f9002001 	str	x1, [x0, #64]
  40130c:	b9005fbf 	str	wzr, [x29, #92]
  401310:	1400000b 	b	40133c <help+0x6c>
  401314:	b9805fa0 	ldrsw	x0, [x29, #92]
  401318:	d37df000 	lsl	x0, x0, #3
  40131c:	910043a1 	add	x1, x29, #0x10
  401320:	f8606821 	ldr	x1, [x1, x0]
  401324:	90000000 	adrp	x0, 401000 <del+0xc0>
  401328:	911f0000 	add	x0, x0, #0x7c0
  40132c:	97fffcd1 	bl	400670 <printf@plt>
  401330:	b9405fa0 	ldr	w0, [x29, #92]
  401334:	11000400 	add	w0, w0, #0x1
  401338:	b9005fa0 	str	w0, [x29, #92]
  40133c:	b9405fa0 	ldr	w0, [x29, #92]
  401340:	7100201f 	cmp	w0, #0x8
  401344:	54fffe8d 	b.le	401314 <help+0x44>
  401348:	d503201f 	nop
  40134c:	a8c67bfd 	ldp	x29, x30, [sp], #96
  401350:	d65f03c0 	ret

0000000000401354 <main>:
  401354:	d110c3ff 	sub	sp, sp, #0x430
  401358:	a9007bfd 	stp	x29, x30, [sp]
  40135c:	910003fd 	mov	x29, sp
  401360:	f90217bf 	str	xzr, [x29, #1064]
  401364:	b90427bf 	str	wzr, [x29, #1060]
  401368:	12800000 	mov	w0, #0xffffffff            	// #-1
  40136c:	b90013a0 	str	w0, [x29, #16]
  401370:	90000000 	adrp	x0, 401000 <del+0xc0>
  401374:	9123a000 	add	x0, x0, #0x8e8
  401378:	97fffcb2 	bl	400640 <puts@plt>
  40137c:	140000dd 	b	4016f0 <main+0x39c>
  401380:	90000000 	adrp	x0, 401000 <del+0xc0>
  401384:	9124a000 	add	x0, x0, #0x928
  401388:	f94217a1 	ldr	x1, [x29, #1064]
  40138c:	97fffcb9 	bl	400670 <printf@plt>
  401390:	97ffffd0 	bl	4012d0 <help>
  401394:	910043a1 	add	x1, x29, #0x10
  401398:	90000000 	adrp	x0, 401000 <del+0xc0>
  40139c:	91250000 	add	x0, x0, #0x940
  4013a0:	97fffcb0 	bl	400660 <__isoc99_scanf@plt>
  4013a4:	b94013a0 	ldr	w0, [x29, #16]
  4013a8:	71000c1f 	cmp	w0, #0x3
  4013ac:	54000900 	b.eq	4014cc <main+0x178>  // b.none
  4013b0:	71000c1f 	cmp	w0, #0x3
  4013b4:	5400010c 	b.gt	4013d4 <main+0x80>
  4013b8:	7100041f 	cmp	w0, #0x1
  4013bc:	540001e0 	b.eq	4013f8 <main+0xa4>  // b.none
  4013c0:	7100041f 	cmp	w0, #0x1
  4013c4:	5400026c 	b.gt	401410 <main+0xbc>
  4013c8:	7100001f 	cmp	w0, #0x0
  4013cc:	540017c0 	b.eq	4016c4 <main+0x370>  // b.none
  4013d0:	140000c2 	b	4016d8 <main+0x384>
  4013d4:	7100141f 	cmp	w0, #0x5
  4013d8:	54000e80 	b.eq	4015a8 <main+0x254>  // b.none
  4013dc:	7100141f 	cmp	w0, #0x5
  4013e0:	54000a4b 	b.lt	401528 <main+0x1d4>  // b.tstop
  4013e4:	7100181f 	cmp	w0, #0x6
  4013e8:	540011a0 	b.eq	40161c <main+0x2c8>  // b.none
  4013ec:	71001c1f 	cmp	w0, #0x7
  4013f0:	540014e0 	b.eq	40168c <main+0x338>  // b.none
  4013f4:	140000b9 	b	4016d8 <main+0x384>
  4013f8:	97fffe30 	bl	400cb8 <creat_tree>
  4013fc:	f90217a0 	str	x0, [x29, #1064]
  401400:	90000000 	adrp	x0, 401000 <del+0xc0>
  401404:	91252000 	add	x0, x0, #0x948
  401408:	97fffc8e 	bl	400640 <puts@plt>
  40140c:	140000b8 	b	4016ec <main+0x398>
  401410:	f94217a0 	ldr	x0, [x29, #1064]
  401414:	f100001f 	cmp	x0, #0x0
  401418:	54000520 	b.eq	4014bc <main+0x168>  // b.none
  40141c:	14000024 	b	4014ac <main+0x158>
  401420:	90000000 	adrp	x0, 401000 <del+0xc0>
  401424:	9125c000 	add	x0, x0, #0x970
  401428:	97fffc92 	bl	400670 <printf@plt>
  40142c:	910053a1 	add	x1, x29, #0x14
  401430:	90000000 	adrp	x0, 401000 <del+0xc0>
  401434:	91250000 	add	x0, x0, #0x940
  401438:	97fffc8a 	bl	400660 <__isoc99_scanf@plt>
  40143c:	b94017a0 	ldr	w0, [x29, #20]
  401440:	7136081f 	cmp	w0, #0xd82
  401444:	54000340 	b.eq	4014ac <main+0x158>  // b.none
  401448:	b94017a2 	ldr	w2, [x29, #20]
  40144c:	b98427a0 	ldrsw	x0, [x29, #1060]
  401450:	d37ef400 	lsl	x0, x0, #2
  401454:	910063a1 	add	x1, x29, #0x18
  401458:	b8206822 	str	w2, [x1, x0]
  40145c:	910063a1 	add	x1, x29, #0x18
  401460:	b98427a0 	ldrsw	x0, [x29, #1060]
  401464:	d37ef400 	lsl	x0, x0, #2
  401468:	8b000020 	add	x0, x1, x0
  40146c:	aa0003e1 	mov	x1, x0
  401470:	f94217a0 	ldr	x0, [x29, #1064]
  401474:	97fffe47 	bl	400d90 <insert>
  401478:	7100001f 	cmp	w0, #0x0
  40147c:	54000121 	b.ne	4014a0 <main+0x14c>  // b.any
  401480:	b94427a0 	ldr	w0, [x29, #1060]
  401484:	11000400 	add	w0, w0, #0x1
  401488:	b90427a0 	str	w0, [x29, #1060]
  40148c:	b94017a1 	ldr	w1, [x29, #20]
  401490:	90000000 	adrp	x0, 401000 <del+0xc0>
  401494:	91270000 	add	x0, x0, #0x9c0
  401498:	97fffc76 	bl	400670 <printf@plt>
  40149c:	14000004 	b	4014ac <main+0x158>
  4014a0:	90000000 	adrp	x0, 401000 <del+0xc0>
  4014a4:	91278000 	add	x0, x0, #0x9e0
  4014a8:	97fffc66 	bl	400640 <puts@plt>
  4014ac:	b94017a0 	ldr	w0, [x29, #20]
  4014b0:	7136081f 	cmp	w0, #0xd82
  4014b4:	54fffb61 	b.ne	401420 <main+0xcc>  // b.any
  4014b8:	1400008d 	b	4016ec <main+0x398>
  4014bc:	90000000 	adrp	x0, 401000 <del+0xc0>
  4014c0:	9127c000 	add	x0, x0, #0x9f0
  4014c4:	97fffc5f 	bl	400640 <puts@plt>
  4014c8:	14000089 	b	4016ec <main+0x398>
  4014cc:	f94217a0 	ldr	x0, [x29, #1064]
  4014d0:	f100001f 	cmp	x0, #0x0
  4014d4:	54000220 	b.eq	401518 <main+0x1c4>  // b.none
  4014d8:	f94217a0 	ldr	x0, [x29, #1064]
  4014dc:	97ffff2a 	bl	401184 <test_structure>
  4014e0:	b90017a0 	str	w0, [x29, #20]
  4014e4:	b94017a0 	ldr	w0, [x29, #20]
  4014e8:	3100041f 	cmn	w0, #0x1
  4014ec:	54000081 	b.ne	4014fc <main+0x1a8>  // b.any
  4014f0:	90000000 	adrp	x0, 401000 <del+0xc0>
  4014f4:	91286000 	add	x0, x0, #0xa18
  4014f8:	97fffc52 	bl	400640 <puts@plt>
  4014fc:	b94017a0 	ldr	w0, [x29, #20]
  401500:	7100001f 	cmp	w0, #0x0
  401504:	54000f21 	b.ne	4016e8 <main+0x394>  // b.any
  401508:	90000000 	adrp	x0, 401000 <del+0xc0>
  40150c:	9128e000 	add	x0, x0, #0xa38
  401510:	97fffc4c 	bl	400640 <puts@plt>
  401514:	14000075 	b	4016e8 <main+0x394>
  401518:	90000000 	adrp	x0, 401000 <del+0xc0>
  40151c:	91292000 	add	x0, x0, #0xa48
  401520:	97fffc48 	bl	400640 <puts@plt>
  401524:	14000071 	b	4016e8 <main+0x394>
  401528:	f94217a0 	ldr	x0, [x29, #1064]
  40152c:	f100001f 	cmp	x0, #0x0
  401530:	54000340 	b.eq	401598 <main+0x244>  // b.none
  401534:	90000000 	adrp	x0, 401000 <del+0xc0>
  401538:	9129a000 	add	x0, x0, #0xa68
  40153c:	97fffc4d 	bl	400670 <printf@plt>
  401540:	910053a1 	add	x1, x29, #0x14
  401544:	90000000 	adrp	x0, 401000 <del+0xc0>
  401548:	91250000 	add	x0, x0, #0x940
  40154c:	97fffc45 	bl	400660 <__isoc99_scanf@plt>
  401550:	b94017a0 	ldr	w0, [x29, #20]
  401554:	2a0003e1 	mov	w1, w0
  401558:	f94217a0 	ldr	x0, [x29, #1064]
  40155c:	97fffde6 	bl	400cf4 <find>
  401560:	f9020fa0 	str	x0, [x29, #1048]
  401564:	f9420fa0 	ldr	x0, [x29, #1048]
  401568:	f100001f 	cmp	x0, #0x0
  40156c:	540000a1 	b.ne	401580 <main+0x22c>  // b.any
  401570:	90000000 	adrp	x0, 401000 <del+0xc0>
  401574:	912a2000 	add	x0, x0, #0xa88
  401578:	97fffc32 	bl	400640 <puts@plt>
  40157c:	1400005c 	b	4016ec <main+0x398>
  401580:	f9420fa0 	ldr	x0, [x29, #1048]
  401584:	b9400001 	ldr	w1, [x0]
  401588:	90000000 	adrp	x0, 401000 <del+0xc0>
  40158c:	912a8000 	add	x0, x0, #0xaa0
  401590:	97fffc38 	bl	400670 <printf@plt>
  401594:	14000056 	b	4016ec <main+0x398>
  401598:	90000000 	adrp	x0, 401000 <del+0xc0>
  40159c:	912b0000 	add	x0, x0, #0xac0
  4015a0:	97fffc28 	bl	400640 <puts@plt>
  4015a4:	14000052 	b	4016ec <main+0x398>
  4015a8:	f94217a0 	ldr	x0, [x29, #1064]
  4015ac:	f100001f 	cmp	x0, #0x0
  4015b0:	540002e0 	b.eq	40160c <main+0x2b8>  // b.none
  4015b4:	f94217a0 	ldr	x0, [x29, #1064]
  4015b8:	97fffeba 	bl	4010a0 <travel>
  4015bc:	b90423bf 	str	wzr, [x29, #1056]
  4015c0:	1400000c 	b	4015f0 <main+0x29c>
  4015c4:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4015c8:	91018000 	add	x0, x0, #0x60
  4015cc:	b98423a1 	ldrsw	x1, [x29, #1056]
  4015d0:	f8617800 	ldr	x0, [x0, x1, lsl #3]
  4015d4:	b9400001 	ldr	w1, [x0]
  4015d8:	90000000 	adrp	x0, 401000 <del+0xc0>
  4015dc:	912b8000 	add	x0, x0, #0xae0
  4015e0:	97fffc24 	bl	400670 <printf@plt>
  4015e4:	b94423a0 	ldr	w0, [x29, #1056]
  4015e8:	11000400 	add	w0, w0, #0x1
  4015ec:	b90423a0 	str	w0, [x29, #1056]
  4015f0:	b0000080 	adrp	x0, 412000 <exit@GLIBC_2.17>
  4015f4:	91017000 	add	x0, x0, #0x5c
  4015f8:	b9400000 	ldr	w0, [x0]
  4015fc:	b94423a1 	ldr	w1, [x29, #1056]
  401600:	6b00003f 	cmp	w1, w0
  401604:	54fffe0b 	b.lt	4015c4 <main+0x270>  // b.tstop
  401608:	14000039 	b	4016ec <main+0x398>
  40160c:	90000000 	adrp	x0, 401000 <del+0xc0>
  401610:	912bc000 	add	x0, x0, #0xaf0
  401614:	97fffc0b 	bl	400640 <puts@plt>
  401618:	14000035 	b	4016ec <main+0x398>
  40161c:	f94217a0 	ldr	x0, [x29, #1064]
  401620:	f100001f 	cmp	x0, #0x0
  401624:	540002c0 	b.eq	40167c <main+0x328>  // b.none
  401628:	90000000 	adrp	x0, 401000 <del+0xc0>
  40162c:	912c4000 	add	x0, x0, #0xb10
  401630:	97fffc04 	bl	400640 <puts@plt>
  401634:	910053a1 	add	x1, x29, #0x14
  401638:	90000000 	adrp	x0, 401000 <del+0xc0>
  40163c:	91250000 	add	x0, x0, #0x940
  401640:	97fffc08 	bl	400660 <__isoc99_scanf@plt>
  401644:	b94017a0 	ldr	w0, [x29, #20]
  401648:	2a0003e1 	mov	w1, w0
  40164c:	f94217a0 	ldr	x0, [x29, #1064]
  401650:	97fffe3c 	bl	400f40 <del>
  401654:	7100001f 	cmp	w0, #0x0
  401658:	540000a1 	b.ne	40166c <main+0x318>  // b.any
  40165c:	90000000 	adrp	x0, 401000 <del+0xc0>
  401660:	912ce000 	add	x0, x0, #0xb38
  401664:	97fffc03 	bl	400670 <printf@plt>
  401668:	14000021 	b	4016ec <main+0x398>
  40166c:	90000000 	adrp	x0, 401000 <del+0xc0>
  401670:	912d4000 	add	x0, x0, #0xb50
  401674:	97fffbf3 	bl	400640 <puts@plt>
  401678:	1400001d 	b	4016ec <main+0x398>
  40167c:	90000000 	adrp	x0, 401000 <del+0xc0>
  401680:	912d8000 	add	x0, x0, #0xb60
  401684:	97fffbef 	bl	400640 <puts@plt>
  401688:	14000019 	b	4016ec <main+0x398>
  40168c:	f94217a0 	ldr	x0, [x29, #1064]
  401690:	f100001f 	cmp	x0, #0x0
  401694:	54000100 	b.eq	4016b4 <main+0x360>  // b.none
  401698:	f94217a0 	ldr	x0, [x29, #1064]
  40169c:	97fffefb 	bl	401288 <remove_tree>
  4016a0:	90000000 	adrp	x0, 401000 <del+0xc0>
  4016a4:	912e0000 	add	x0, x0, #0xb80
  4016a8:	97fffbe6 	bl	400640 <puts@plt>
  4016ac:	f90217bf 	str	xzr, [x29, #1064]
  4016b0:	1400000f 	b	4016ec <main+0x398>
  4016b4:	90000000 	adrp	x0, 401000 <del+0xc0>
  4016b8:	912e8000 	add	x0, x0, #0xba0
  4016bc:	97fffbe1 	bl	400640 <puts@plt>
  4016c0:	1400000b 	b	4016ec <main+0x398>
  4016c4:	90000000 	adrp	x0, 401000 <del+0xc0>
  4016c8:	912f2000 	add	x0, x0, #0xbc8
  4016cc:	97fffbdd 	bl	400640 <puts@plt>
  4016d0:	52800000 	mov	w0, #0x0                   	// #0
  4016d4:	97fffbc7 	bl	4005f0 <exit@plt>
  4016d8:	90000000 	adrp	x0, 401000 <del+0xc0>
  4016dc:	912f6000 	add	x0, x0, #0xbd8
  4016e0:	97fffbd8 	bl	400640 <puts@plt>
  4016e4:	14000002 	b	4016ec <main+0x398>
  4016e8:	d503201f 	nop
  4016ec:	b90017bf 	str	wzr, [x29, #20]
  4016f0:	b94013a0 	ldr	w0, [x29, #16]
  4016f4:	7100001f 	cmp	w0, #0x0
  4016f8:	54ffe441 	b.ne	401380 <main+0x2c>  // b.any
  4016fc:	52800000 	mov	w0, #0x0                   	// #0
  401700:	a9407bfd 	ldp	x29, x30, [sp]
  401704:	9110c3ff 	add	sp, sp, #0x430
  401708:	d65f03c0 	ret
  40170c:	00000000 	.inst	0x00000000 ; undefined

0000000000401710 <__libc_csu_init>:
  401710:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  401714:	910003fd 	mov	x29, sp
  401718:	a901d7f4 	stp	x20, x21, [sp, #24]
  40171c:	90000094 	adrp	x20, 411000 <__FRAME_END__+0xf414>
  401720:	90000095 	adrp	x21, 411000 <__FRAME_END__+0xf414>
  401724:	91374294 	add	x20, x20, #0xdd0
  401728:	913722b5 	add	x21, x21, #0xdc8
  40172c:	a902dff6 	stp	x22, x23, [sp, #40]
  401730:	cb150294 	sub	x20, x20, x21
  401734:	f9001ff8 	str	x24, [sp, #56]
  401738:	2a0003f6 	mov	w22, w0
  40173c:	aa0103f7 	mov	x23, x1
  401740:	9343fe94 	asr	x20, x20, #3
  401744:	aa0203f8 	mov	x24, x2
  401748:	97fffb9c 	bl	4005b8 <_init>
  40174c:	b4000194 	cbz	x20, 40177c <__libc_csu_init+0x6c>
  401750:	f9000bb3 	str	x19, [x29, #16]
  401754:	d2800013 	mov	x19, #0x0                   	// #0
  401758:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  40175c:	aa1803e2 	mov	x2, x24
  401760:	aa1703e1 	mov	x1, x23
  401764:	2a1603e0 	mov	w0, w22
  401768:	91000673 	add	x19, x19, #0x1
  40176c:	d63f0060 	blr	x3
  401770:	eb13029f 	cmp	x20, x19
  401774:	54ffff21 	b.ne	401758 <__libc_csu_init+0x48>  // b.any
  401778:	f9400bb3 	ldr	x19, [x29, #16]
  40177c:	a941d7f4 	ldp	x20, x21, [sp, #24]
  401780:	a942dff6 	ldp	x22, x23, [sp, #40]
  401784:	f9401ff8 	ldr	x24, [sp, #56]
  401788:	a8c47bfd 	ldp	x29, x30, [sp], #64
  40178c:	d65f03c0 	ret

0000000000401790 <__libc_csu_fini>:
  401790:	d65f03c0 	ret

Disassembly of section .fini:

0000000000401794 <_fini>:
  401794:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401798:	910003fd 	mov	x29, sp
  40179c:	a8c17bfd 	ldp	x29, x30, [sp], #16
  4017a0:	d65f03c0 	ret
